Field of the Invention
The invention relates to a two-stage operational amplifier having an input stage whose input can be supplied with a signal that is to be amplified and whose output provides a first amplified signal. The amplifier further has an output stage whose input side is connected to the output of the input stage and at whose output a second amplified signal can be derived.
A configuration of the generic type is specified in Japanese Patent Abstract JP 11088070 A, for example. This document specifies an amplifier circuit having an input stage supplied by a first supply voltage and a downstream output stage supplied by a second supply voltage, where the second supply voltage is higher than the first supply voltage.
The printed document by Tietze, Schenk, titled xe2x80x9cHalbleiter-Schaltungstechnik [Semiconductor Circuitry]xe2x80x9d, 9th edition 1990, pages 542-546 specifies integrated voltage regulators for providing a stabilized DC voltage.
Standard CMOS technology normally features a low withstand voltage within specified limits. For higher voltages, such as can arise on application specific integrated circuit (ASIC) interfaces, high-voltage CMOS technology is suitable, by way of example, but a feature of this is an increased chip area requirement, and also it cannot be integrated in a conventional standard CMOS production process without additional complexity.
There is also high-voltage bipolar transistor technology. However, an operational amplifier constructed entirely or predominantly from high-voltage bipolar transistors has a large area requirement, a low phase reserve on account of the high parasitic capacitances of high-voltage bipolar transistors, a large amplifier offset, caused by the relatively low current gain, and a relatively poor power supply rejection ratio (PSRR), which is likewise caused by the high parasitic capacitances.
Another two-stage operational amplifier of the generic type, in the form of a class AB rail-to-rail operational amplifier, is specified, by way of example, in the reference titled xe2x80x9cDesign of Low-Voltage, Low-Power Operational Amplifier Cellsxe2x80x9d, by Ron Hogervorst et al., Cluver Academic Publishers, Boston, on page 151.
It is accordingly an object of the invention to provide a two-stage operational amplifier which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which is suitable for high output voltages and has a good PSRR response.
With the foregoing and other objects in view there is provided, in accordance with the invention, a two-stage operational amplifier. The amplifier contains an input stage having an input for receiving a signal to be amplified and an output providing a first amplified signal, an output stage having an input side connected to the output of the input stage and an output providing a second amplified signal, and a voltage regulator having an output connected to the input stage and supplying the input stage with a first supply potential. The voltage regulator further has an input connected to the output stage and supplies the output stage with a second supply potential. The output stage has at least one output transistor and a quiescent-current setting circuit provided for the output transistor. The quiescent-current setting circuit is connected to the output of the voltage regulator and receives the first supply potential.
The object is achieved with a two-stage operational amplifier as cited in the introduction in which the device for voltage reduction, in the form of a voltage regulator, is provided. The voltage regulator has an output connected to the input stage in order to supply the latter with a first supply potential and whose input is connected to the output stage and supplies a second supply potential. The output stage has a quiescent-current setting circuit for at least one output transistor in the output stage, the quiescent-current setting circuit being connected to the first supply potential in order to receive a voltage.
The operational amplifier can have more than two stages.
The magnitude of the first supply potential supplying the input stage is smaller than that of the second supply potential supplying the output stage.
The supply of voltage to the output stage being a higher, second supply potential has the advantage that it is possible to combine various technologies, for example standard CMOS technology and high-voltage bipolar technology, within one operational amplifier. A two-stage operational amplifier developed in this manner can largely be constructed using standard MOS transistors, can be produced using relatively little chip area and with a good PSRR response, and is suitable for high output voltages.
To improve the operational amplifier further, inter alia with regard to power consumption and area requirement, not only the input stage and the quiescent-current setting circuit for at least one output transistor in the output stage but also other circuit parts in the output stage can be supplied with the lower, first supply potential.
To derive the lower, first supply potential from the higher, second supply potential, the device for voltage reduction can be in the form of an internal voltage regulation circuit which can be optimized in terms of the PSRR and the first supply potential""s voltage stabilization, so that, in the event of the occurrence of interference pulses at the level of the second supply potential, only negligibly small disturbances are overcoupled onto lines carrying the first supply potential, and again only a small portion of these disturbances spreads to the input stage of the two-stage operational amplifier.
Whereas the second supply potential can be situated in a range from xe2x88x9218 V to +25 V, the first supply potential derived therefrom, whose magnitude is smaller than that of the second supply potential, is +3 volts, for example. In many applications-specific integrated circuits (ASICs), such a low internal chip supply voltage of, for example, +3 volts, which is an improvement in terms of PSSR and voltage stabilization, is already present anyway for the signal-processing CMOS circuit parts of the ASIC, which results in that the two-stage operational amplifier described can be produced with the least possible complexity while providing effective suppression of disturbances related to the supply of power.
In one preferred embodiment of the invention, the input stage features a differential amplifier, to which the signal to be amplified can be supplied, and a convoluted cascode circuit connected downstream of the differential amplifier. Since the cascode circuit is provided in the input stage of the two-stage operational amplifier, which input stage can be operated at the lower, first supply potential, the cascode circuit can be produced with a small chip area, with low parasitic capacitances and with a higher PSRR. The cascode circuit described also allows low input signal potentials to be processed and allows PMOS transistors to be used. The signal that can be tapped off on the output side of the cascode circuit is simultaneously the input signal for the output stage of the two-stage operational amplifier.
In another advantageous embodiment of the present invention, the output stage features a respective quiescent-current setting circuit which is provided for a respective output transistor, among which a first output transistor is connected to the second supply potential and a second output transistor is connected to a reference-ground potential. The quiescent-current setting described for the output stage of the two-stage operational amplifier allows a reduction of transfer distortions in the second amplified signal that can be derived on the output side of the output stage. In addition, the quiescent-current setting can ensure the stability of any desired output voltages and of load resistors of any desired value in applications in which the operational amplifier is operated using feedback networks.
In another advantageous embodiment of the present invention, the quiescent-current setting circuit for the second output transistor is connected to the first supply potential in order to supply it with voltage. Although the output stage is operated by the higher, second supply potential, the quiescent-current setting circuit for the second output transistor can be supplied with the lower, first supply potential, which results in that the quiescent-current setting circuit for the second output transistor can be produced using little chip area and standard NMOS components.
In another advantageous embodiment of the present invention, the quiescent-current setting circuit for the first output transistor is connected to the first supply potential in order to supply it with voltage. In this case, the description already given for the quiescent-current setting circuit for the second output transistor applies to the quiescent-current setting circuit for the first output transistor; the result is likewise a quiescent-current setting circuit which can be produced with little chip area requirement and using standard PMOS components.
In another preferred embodiment of the present invention, bipolar transistors are provided which are connected first to the quiescent-current setting circuit for the first output transistor and second to the second supply potential. As an alternative to supplying the quiescent-current setting circuit for the output transistor with the first supply potential, it can be supplied with the second supply potential using bipolar transistors which are connected between the quiescent-current setting circuit for the first output transistor and the second, higher supply potential. In this case, the bipolar transistors form a virtual potential, corresponding to the first, low supply potential, at their connecting nodes in the quiescent-current setting circuit for the first output transistor. As a result of this, the quiescent-current setting circuit for the first output transistor can also be produced with standard PMOS components having the above-mentioned advantages. In this configuration, the bipolar transistors protect the PMOS transistors from the higher voltage. To this end, the base connections of the bipolar transistors can be connected to a suitable potential. In this case, the bipolar transistors form a translinear loop with the MOS transistors in the quiescent-current setting circuit for the purpose of setting quiescent current. The amplifier configuration is suitable for operation using a particularly low first supply potential.
In another advantageous embodiment of the present invention, to generate a base potential for the bipolar transistors in the quiescent-current setting circuit, a circuit section is provided which is connected to the base connections of the bipolar transistors. Using the first and/or second supply potential, further transistors can easily be used to form a base potential on the bipolar transistors in a quiescent-current setting circuit, which base potential protects the quiescent-current setting circuit from the high, second supply potential.
In another advantageous embodiment of the present invention, to actuate the output transistors, a respective current-mirror transistor is connected to a respective output transistor so as to form a respective current mirror, the current mirrors being able to be supplied with the first amplified signal in order to actuate them. In this case, the current mirrors allow independent setting of a mirror ratio that can differ for the first and second output transistors.
In another advantageous embodiment of the present invention, to actuate the two current mirrors, a respective driver transistor is connected to a respective current-mirror transistor, the input side of the driver transistors being connected to the output of the input stage. The driver transistors can be standard MOS transistors. Together with a respective quiescent-current setting circuit and a respective output transistor, a respective driver transistor forms a mixed translinear loop with the aim of subjecting the high-impedance outputs of the input stage to as little capacitance or resistance as possible. This improves the phase reserve and the linear gain of the two-stage operational amplifier, and the systematic offset is reduced.
In another advantageous embodiment of the present invention, the driver transistors are MOS transistors, preferably standard MOS transistors, and the current-mirror and output transistors are bipolar transistors, preferably bipolar transistors having a high withstand voltage.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a two-stage operational amplifier, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.